Small processors manage work around the GPU
Modern Nvidia graphics processors contain far more computing cores than the CUDA and shader units familiar to developers. Depending on the chip, Nvidia estimates that roughly 10 to 40 internal RISC-V processors handle management functions around the main graphics hardware.
These are not general-purpose CPUs exposed to application programmers. They operate as embedded controllers for tasks including video encoding and decoding, power management, security and graphics-system coordination. Some execute cryptographically verified firmware and participate in the chain that decides whether GPU firmware can start.
Nvidia previously used its proprietary Falcon controller architecture for many of these jobs. Falcon first appeared around the G98 generation, replacing earlier Tensilica-based video controllers. By 2016, more than 15 engines on a single chip could use Falcon processors. Their design favored small die area and tolerance for memory latency, but their 32-bit address space, lack of a data cache and inability to run a conventional operating system became constraints as GPU management grew more complex.
The company evaluated licensed architectures and an updated in-house design before selecting RISC-V’s instruction set. Nvidia’s resulting controller reportedly delivered about three times Falcon’s performance in twice the area, while allowing the company to build extensions around its own requirements.
A custom ecosystem inside each chip
Nvidia now uses several internal designs. These include 32-bit and 64-bit RISC-V cores as well as a version paired with a wide vector unit for deep-learning acceleration. A reusable subsystem called Peregrine can combine a controller with cache, tightly coupled memory, direct-memory access and cryptographic blocks.
The GPU System Processor is among the most consequential deployments. It groups four 64-bit cores with memory isolation, interrupt handling, a host interface, mailbox and coherent connection across the GPU. Since 2018, that processor has taken over substantial control work that previously sat in the host graphics driver. Moving those responsibilities onto the device can make the GPU more self-contained, although users still cannot directly program the management cores.
Nvidia’s open kernel modules provide a public glimpse of the architecture. A controller list in the driver source includes both older Falcon units and numerous RISC-V engines associated with the system processor, power-management unit and video-decoding blocks. Headers also point to continued RISC-V use in later GPU generations.
A Nvidia engineering executive estimated in 2024 that the company was shipping between one and two billion of these cores annually. That was described as an unofficial estimate rather than an audited shipment figure, but it illustrates how embedded deployments can reach enormous scale without appearing as standalone processors. The RISC-V cores inside a GPU are largely invisible to buyers, yet they have become an essential control layer supporting the much larger engines that render graphics and run accelerated computing workloads.
